Custom Wrapper

Implementing the CustomWrapper

The CustomWrapper entity defines the interface that custom designs need to implement, as well as a simple abstraction from the instrument slot. Note when using Verilog, the wrapper needs to be declared before proceeding to define the custom architecture. For ease of use, this wrapper declaration is automatically generated whenever a new Verilog file is created.

WARNING

In the Verilog CustomWrapper, it is recommended not to modify the module declaration. While a bitstream may still be generated if the module definition is changed, it might not behave as expected.

Implementing the CustomWrapper interface simply requires defining an architecture.

CustomWrapper Architecture

WARNING

Only one architecture should implement CustomWrapper per project. If multiple architectures exist, the one that is synthesized is undefined.

Wrapper Ports

The details of input, output and clock use is platform specific. For details, see Input and Output.

Control Registers

These provide control of custom designs at runtime. See Control Registers.