VHDL coding template

Provided is a blank template for creating HDL files using the Moku Cloud Compile.

Entity Ports

Port	In/Out	Type	Range
Clk	in	std_logic	-
Reset	in	std_logic	-
InputA	in	signed	15 downto 0
InputB	in	signed	15 downto 0
InputC (Moku:Pro only)	in	signed	15 downto 0
InputD (Moku:Pro only)	in	signed	15 downto 0
ExtTrig (Moku:Lab and Moku:Pro)	in	std_logic	-
OutputA	out	signed	15 downto 0
OutputB	out	signed	15 downto 0
OutputC (Moku:Go and Moku:Pro)	out	signed	15 downto 0
OutputD (Moku:Pro only)	out	signed	15 downto 0
Control0	in	std_logic_vector	31 downto 0
Control1	in	std_logic_vector	31 downto 0
...	...	...	...
Control15	in	std_logic_vector	31 downto 0

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Numeric_Std.all;


architecture Behavioural of CustomWrapper is
begin
    -- ___ <= InputA;
    -- ___ <= InputB;
    -- ___ <= InputC;
    -- ___ <= InputD;

    -- ___ <= Control0;
    -- ___ <= Control1;
    -- ___ <= Control2;
    --      ...
    -- ___ <= Control15;

    -- OutputA => ___;
    -- OutputB => ___;
    -- OutputC => ___;
    -- OutputD => ___;
end architecture;