# FPGA coding template

Provided are blank templates for creating HDL designs using Moku Cloud Compile, supporting CustomWrapper, CustomInstrument, and CustomInstrumentInterlaced. The CustomWrapper is a legacy entity used for MokuOS versions prior to 4.1.1 and has since been replaced by CustomInstrument. The CustomInstrumentInterlaced entity enables interleaving, a technique that allows access to the full sampling rate capability of the Moku device in Multi-Instrument Mode.

# CustomInstrument Template

Port	In/Out	Type	Range	Array size
Clk	in	std_logic	-	-
Reset	in	std_logic	-	-
Sync	in	std_logic_vector	31 downto 0	-

InputA	in	signed	15 downto 0	-
InputB	in	signed	15 downto 0	-
InputC^*	in	signed	15 downto 0	-
InputD^*	in	signed	15 downto 0	-

ExtTrig^**	in	std_logic	-	-

OutputA	out	signed	15 downto 0	-
OutputB	out	signed	15 downto 0	-
OutputC^*	out	signed	15 downto 0	-
OutputD^*	out	signed	15 downto 0	-

Control	in	array_of_slv	31 downto 0	0 to 15

Status	out	array_of_slv	31 downto 0	0 to 15

^*Refer to block diagram for details on where the inputs and outputs are connected.

^**Available only on Moku:Lab, Moku:Pro and Moku:Delta

# CustomInstrumentInterlaced Template

Port	In/Out	Type	Range	Array size
Clk	in	std_logic	-	-
Reset	in	std_logic	-	-
Sync	in	std_logic_vector	31 downto 0	-

InputA	in	array_of_signed	15 downto 0	0 to interlacingfactor^*** - 1
InputB	in	array_of_signed	15 downto 0	0 to interlacingfactor^*** - 1
InputC^*	in	array_of_signed	15 downto 0	0 to interlacingfactor^*** - 1
InputD^*	in	array_of_signed	15 downto 0	0 to interlacingfactor^*** - 1

ExtTrig^**	in	std_logic	-	-

OutputA	out	array_of_signed	15 downto 0	0 to interlacingfactor^*** - 1
OutputB	out	array_of_signed	15 downto 0	0 to interlacingfactor^*** - 1
OutputC^*	out	array_of_signed	15 downto 0	0 to interlacingfactor^*** - 1
OutputD^*	out	array_of_signed	15 downto 0	0 to interlacingfactor^*** - 1

Control	in	array_of_slv	31 downto 0	0 to 15

Status	out	array_of_slv	31 downto 0	0 to 15

^*Refer to block diagram for details on where the inputs and outputs are connected.

^**Available only on Moku:Lab, Moku:Pro and Moku:Delta

^***Refer to interlacing for details on the available interlacing factors

# CustomWrapper Template

Port	In/Out	Type	Range
Clk	in	std_logic	-
Reset	in	std_logic	-
Sync	in	std_logic_vector	31 downto 0

InputA	in	signed	15 downto 0
InputB	in	signed	15 downto 0
InputC^*	in	signed	15 downto 0
InputD^*	in	signed	15 downto 0

ExtTrig^**	in	std_logic	-

OutputA	out	signed	15 downto 0
OutputB	out	signed	15 downto 0
OutputC^*	out	signed	15 downto 0
OutputD^*	out	signed	15 downto 0

Control0	in	std_logic_vector	31 downto 0
Control1	in	std_logic_vector	31 downto 0
...	...	...	...
Control15	in	std_logic_vector	31 downto 0

^*Refer to block diagram for details on where the inputs and outputs are connected.

^**Available only on Moku:Lab, Moku:Pro and Moku:Delta

← Bitstream Browser Basic →