Control Registers

The wrapper entity provides 16 Control registers which can be used to control the behavior of the custom design at runtime. For the CustomInstrument entity, the registers are defined as an array of 32-bit std_logic_vectors. For the CustomWrapper entity, the registers are labelled Control0 through to Control15 and are all 32 bit std_logic_vectors.

Type Casting

These Controls can be assigned to various signals in a custom design. With VHDL code, assigning using Controls will often require casting to another type or resizing or both. When using Verilog, the casting and resizing is often implicit during the assignment and is done automatically.